The present invention relates generally semiconductor devices and more particularly an improved semiconductor contact and method of forming the same.
As is known in the art, dynamic random access memories (DRAMs) are used extensively in a wide range of applications. A DRAM typically includes an array of memory cells, each cell comprising a pass transistor, typically a metal oxide semiconductor field effect transistor (MOSFET), coupled in series with a capacitor.
A portion 10 of an array is shown in FIG. 1, which illustrates a complementary pair of bitlines BL and BLxe2x80x2. While this figure only illustrates eight memory cells, it is known to fabricate DRAMs with over one billion cells. The bitline pair BL and BLxe2x80x2 is coupled to equalization/precharge circuitry and a sense amplifier, collectively labeled 12. Although not illustrated, many bitline pairs (and respective circuitry 12) will be provided.
Each memory cell includes a pass transistor 14 coupled in series with a capacitor 16. As shown in the figure, one source/drain region of transistor 14 is coupled to the bitline BL (or BLxe2x80x2). The other source/drain region is coupled to one of the plates of respective capacitor 16. The other plate of capacitor 16 is coupled to a common plate reference voltage.
To select a particular memory cell, a select voltage is applied to one of the wordlines WL0-WL7. As illustrated in FIG. 1, the gate of each pass transistor 14 is coupled to one of the wordlines WL0-WL7. Each wordline will also extend across other bitline pairs (not shown) and couple to the gates of pass transistors of those bitlines. The bitline pair BL and BLxe2x80x2 is selected by applying a select voltage to the select transistors 18 and 18xe2x80x2. When the select transistors 18 and 18xe2x80x2 are selected, the differential voltage signal across the bitline pair will be transferred to input/output lines I/O and I/Oxe2x80x2.
FIG. 2 illustrates two DRAM cells 20a and 20b, which might correspond to the pair of cells circled in FIG. 1. Each of the cells 20a and 20b is formed in a silicon body 22 and includes a pass transistor 14 and a capacitor 16. The pass transistor 14 includes a drain region 24 that is separated from a source 26 by a channel region 28. In this case, the two transistors share a common source region 26.
A gate region, including layers 30 and 32, is disposed over channel region 28 and separated therefrom by gate dielectric 34. In this example, the gate region includes a polysilicon layer 30 and a silicide layer 32. The gate region 30/32 will serve as a wordline. A dielectric layer 36, for example a nitride hard mask, overlies the gate 30/32. An insulating layer 38 overlies both memory cells 20a and 20b. 
The drain region 24 of each transistor is coupled to a capacitor 16. In this figure, capacitor 16 is drawn schematically. As is known in the art, capacitor 16 may be a trench capacitor, i.e., formed within a trench in semiconductor body 22, or a stack capacitor, i.e., formed from two conductor plates that overlie semiconductor body 22.
Common source region 26 is coupled to bit line 38 through a bit line contact 40. Bit line contact 40, sometimes referred to as a plug, passes vertically through insulating layer 38 between the laterally spaced, adjacent gate electrodes 30/32. It should be noted that the wordlines run beneath and perpendicular to the direction of the bitline 40. Further, the bitline contact 42 occupies the space between the adjacent wordlines 30/32. Since the contact 42 is separated from gate regions 30/32 by only a thin dielectric 44, a parasitic capacitor is formed between the two conductive regions.
In DRAM development, dimensions such as the device size and storage cell area are getting smaller with each generation of memory systems. As a result, the storage capacitance is becoming smaller and therefore ratio between bitline to wordline capacitance and storage capacitance becomes more significant in the performance of the cell. For example, bitline to wordline capacitance creates noise which makes it difficult to sense the charge in the storage capacitor. Several techniques have been suggested to reduce the capacitance between the bitline and the wordline. Each of these techniques, however, require additional process and fabrication steps thereby increasing the cost of the memory.
In one aspect, the present invention discloses a transistor device that includes first and second source/drain regions disposed in a semiconductor body and separated by a channel region. A dielectric layer overlies the channel region and a gate electrode overlies the dielectric layer. In the preferred embodiment, the gate electrode includes a polysilicon layer that extends a first lateral distance over the dielectric layer and a silicide layer that extends a second lateral distance over the dielectric layer. In this example, the first lateral distance is greater than the second lateral distance.
This transistor device could be used as a pass transistor of a DRAM cell. For example, two such transistors could share a common source/drain region. A contact would be coupled to the common source/drain region and extend upward between the gate electrodes of the two transistors. Each of these gate electrodes would include two conductors, which could be polysilicon and a silicide. The distance between one of the two conductors and the contact would be greater than the distance between the second conductor and the contact.
Increasing the distance between a conductor and the contact is advantageous since it lowers the capacitance between those two elements. For example, in a DRAM a parasitic capacitance between the wordline and the bitline causes noise in the system and could lead to misinterpretations of the read voltage at the sense amplifier. This embodiment of the invention should help to reduce this problem.
The present invention also provides examples of how such a transistor device could be formed. For example, in one embodiment a composite gate layer is formed over a dielectric layer. The composite gate layer includes a first conductive layer (e.g., polysilicon) and a second conductive layer (e.g., a silicide such as tungsten silicide). A mask layer (e.g., Si3N4) is formed over the composite gate layer and patterned and etched. The composite gate layer is then patterned and etched using the mask layer as a mask. An undercut etch can then be performed so that a portion of the second conductive layer (e.g., WSix) beneath the mask layer is removed.